im.c File Reference

Interruption management (enable/disable) implementation. More...

#include <msp430f2274.h>
#include "im.h"

Include dependency graph for im.c:

Go to the source code of this file.

Macros
#define	IM_DISABLE_1   0
	Interrupts 1 that can be disabled. More...
#define	IM_DISABLE_2   (0x01 || 0x02 || 0x04 || 0x08)
	Interrupts 2 that can be disabled. More...
#define	IM_DISABLE_P1   0xFF
	Interrupts Port1 that can be disabled. More...
#define	IM_DISABLE_P2   0xFF
	Interrupts Port2 that can be disabled. More...
#define	IM_DISABLE_ADC10   TRUE
	Interrupt on ADC10. More...
#define	IM_DISABLE_TA   TRUE
	Interrupt on Timer_A3. More...
#define	IM_DISABLE_TB   FALSE
	Interrupt on Timer_B3. More...

Functions
void	im_disable_interrupt ()
	Disable interrupt. More...
void	im_enable_interrupt ()
	Enable interrupt. More...

Variables
uint8_t	im_saveIE1
	Saved state of IE1.
uint8_t	im_saveIE2
	Saved state of IE2.
uint8_t	im_saveIEP1
	Saved state of Port 1 IE.
uint8_t	im_saveIEP2
	Saved state of Port 2 IE.
uint8_t	im_saveIEOthers
	Saved state of ADC10/Timer_A3/Timer_B3 IE. More...
uint8_t	im_disableCounter

Detailed Description

Interruption management (enable/disable) implementation.

This file implements the management of interrupt enable to make it easy to disable all interrupts but the ones that should remain active. It saves the interrupts that are disabled to enable it again upon request.

Definition in file im.c.

Macro Definition Documentation

#define IM_DISABLE_1   0

Interrupts 1 that can be disabled.

The interrupts here are disabled on request. Each bit is one interrupt. The MSP430F2274 interruption bits are as below:

• Watchdog timer: 0 => 0x01
• Oscillator fault: 1 => 0x02
• (Non)maskable interrupt: 4 => 0x10
• Flash access violation: 5 => 0x20

Definition at line 50 of file im.c.

Referenced by im_disable_interrupt().

#define IM_DISABLE_2   (0x01 || 0x02 || 0x04 || 0x08)

Interrupts 2 that can be disabled.

The interrupts here are disabled on request. Each bit is one interrupt. The MSP430F2274 interruption bits are as below:

• USCI_A0 receive: 0 => 0x01
• USCI_A0 transmit: 1 => 0x02
• USCI_B0 receive: 2 => 0x04
• USCI_B0 transmit: 3 => 0x08

Definition at line 62 of file im.c.

Referenced by im_disable_interrupt().

#define IM_DISABLE_ADC10   TRUE

Interrupt on ADC10.

True if ADC10IE is disabled on request, false otherwise.

Definition at line 85 of file im.c.

Referenced by im_disable_interrupt().

#define IM_DISABLE_P1   0xFF

Interrupts Port1 that can be disabled.

The interrupts here are disabled on request. Each bit is one port pin.

Definition at line 70 of file im.c.

Referenced by im_disable_interrupt().

#define IM_DISABLE_P2   0xFF

Interrupts Port2 that can be disabled.

The interrupts here are disabled on request. Each bit is one port pin.

Definition at line 78 of file im.c.

Referenced by im_disable_interrupt().

#define IM_DISABLE_TA   TRUE

Interrupt on Timer_A3.

True if TAIE is disabled on request, false otherwise.

Definition at line 92 of file im.c.

Referenced by im_disable_interrupt().

#define IM_DISABLE_TB   FALSE

Interrupt on Timer_B3.

True if TBIE is disabled on request, false otherwise.

Definition at line 99 of file im.c.

Referenced by im_disable_interrupt().

Variable Documentation

uint8_t im_saveIEOthers

Saved state of ADC10/Timer_A3/Timer_B3 IE.

Each interrupt in one bit as follows:

• ADC10 IE: 0 => 0x01;
• Timer_A3 IE: 1 => 0x02;
• Timer_B3 IE: 2 => 0x04;

Definition at line 145 of file im.c.

Referenced by im_disable_interrupt(), and im_enable_interrupt().